@conference{Pinyotrakool2020,

title = {Design of a Low Power Processor for Embedded System Applications},

author = {K Pinyotrakool and B Supmonchai},

url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85084995733&doi=10.1109%2fiEECON48109.2020.229544&partnerID=40&md5=f8c88d32a4e07366d1557fed847436bb},

doi = {10.1109/iEECON48109.2020.229544},

isbn = {9781728130767},

year  = {2020},

date = {2020-01-01},

journal = {2020 8th International Electrical Engineering Congress, iEECON 2020},

publisher = {Institute of Electrical and Electronics Engineers Inc.},

abstract = {A low power processor for embedded systems is designed and implemented. The proposed processor can operate on RV32E instruction set architecture using a modified MIPS micro-architecture. Clock gating technique and Standby mode are applied to reduce power consumption. The design is first entered and simulated at RTL using Verilog® to check its functionality, then translated, mapped, and optimized into a 180 nm CMOS technology using cell design library. The resulting layout of the processor is validated against the design at RTL to prove its correctness. The total area of the layout is about 285 μm by 285 μm, which is equivalent to about 7800 gates. For performance, the proposed processor can operate at a maximum clock frequency of 32 MHz, with an average current consumption of 189 μA in normal mode and 11.1 μA in standby state for a supply of 1.8V, or about 5.68 μW/MHz. In comparison with previous work, our proposed processor consumes much less power significantly. © 2020 IEEE.},

note = {cited By 0; Conference of 8th International Electrical Engineering Congress, iEECON 2020 ; Conference Date: 4 March 2020 Through 6 March 2020; Conference Code:159522},

keywords = {},

pubstate = {published},

tppubtype = {conference}

}

@conference{Pamod2019,

title = {An input capacitor-less boost converter with variation-tolerant MPPT circuit for thermal energy harvesting},

author = {J Pamod and S Pumrin and B Supmonchai},

url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85062236418&doi=10.1109%2fECTICon.2018.8619936&partnerID=40&md5=b5a5d392625ae9800ba2a128c03f8209},

doi = {10.1109/ECTICon.2018.8619936},

isbn = {9781538635551},

year  = {2019},

date = {2019-01-01},

journal = {ECTI-CON 2018 - 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology},

pages = {632-635},

publisher = {Institute of Electrical and Electronics Engineers Inc.},

abstract = {This paper presents an input capacitor-less boost converter with a maximum power point tracking (MPPT) circuit for thermal energy harvesting applications. The MPPT circuit is implemented by a fractional open-circuit voltage method with a feedback control circuit to adjust switching frequency of the boost converter until the output power is maximized. The use of a fractional open-circuit voltage method with feedback mechanism make the MPPT highly robust against process variation and component tolerances. Moreover, due to an input capacitor-less feature, the MPPT circuit can fast track the maximum power point (MPP) when input voltage varies. The converter is designed using a 130 nm CMOS technology and uses a thermoelectric generator (TEG) as an input voltage source. Simulation results show a peak efficiency of 68% at 100 mV input voltage and can provide a maximum output voltage of 2.8 V. © 2018 IEEE},

note = {cited By 0; Conference of 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2018 ; Conference Date: 18 July 2018 Through 21 July 2018; Conference Code:144486},

keywords = {},

pubstate = {published},

tppubtype = {conference}

}

@conference{Chokchalermwat2018,

title = {Design of a CMOS Low-Power Limiting Amplifier with RSSI Integrated Circuit for Low-Frequency Wake-Up Receivers},

author = {P Chokchalermwat and B Supmonchai},

url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85066616138&doi=10.1109%2fIEECON.2018.8712225&partnerID=40&md5=3644e39cab031e0205a56fa41a77ec85},

doi = {10.1109/IEECON.2018.8712225},

isbn = {9781538623176},

year  = {2018},

date = {2018-01-01},

journal = {iEECON 2018 - 6th International Electrical Engineering Congress},

publisher = {Institute of Electrical and Electronics Engineers Inc.},

abstract = {This paper presents the circuit level design of a CMOS low power limiting amplifier with received signal strength indicator (RSSI) for low frequency application. The design utilizes a five-stage cascade amplifier with PMOS double diode-connected load for the limiting amplifier and a successive detection log amp for the RSSI structure. DC feedback technique is employed to suppress the DC offset at the output. The proposed circuit is laid out in pmb0.13 mumathbfm CMOS technology, then extracted and simulated. It occupies a minimal active area of 0.0084 mm2and is able to operate within a frequency range of 17 kHz to 166 kHz with an RSSI error less than 2dB, while consumes only pmb1.96mumathbfA current. It also achieves the -3dB input sensitivity of less than pmb12mumathbfV-mathbfrms for a typical dynamic range of 81.7 dB, and a maximum settling time of pmb236 pmbmumathbfs. Compared with best performer circuits, our design has the lowest power consumption while other performance aspects are comparable or better. © 2018 IEEE.},

note = {cited By 1; Conference of 6th International Electrical Engineering Congress, iEECON 2018 ; Conference Date: 7 March 2018 Through 9 March 2018; Conference Code:148002},

keywords = {},

pubstate = {published},

tppubtype = {conference}

}